KAISERSLAUTERN, Germany, Oct. 06, 2026 (GLOBE NEWSWIRE) — LUBIS EDA GmbH, empowering chip design teams to achieve high-confidence RTL sign-off through expert formal verification services and proven methodology, today announced FormalOS: a verification infrastructure platform designed to make formal verification more systematic, scalable and predictable.
FormalOS provides a tool-agnostic orchestration layer for the verification flow, unifying formal engines, apps and other tools into a single environment. Built on the LUBIS Proven Process, it gives design teams the infrastructure to apply formal verification systematically and at scale, supporting more predictable, high-confidence sign-off.
The platform brings together:
- Structured workflows
- Mature methodology
- Proprietary verification playbooks
- Automated formal apps and tools
- Verification IP (VIP)
- AI integration (optional)
- Sign-off evidence
Formal verification can provide exhaustive evidence of design correctness where simulation cannot, but scaling its use has traditionally depended heavily on scarce individual expertise and manual workflows. FormalOS provides infrastructure to codify that expertise and apply it consistently — not only throughout the verification flow, but also across projects, teams and tools.
“As AI makes RTL faster and easier to generate, establishing confidence in that RTL becomes even more important,” said Dr. Tobias Ludwig, CEO and co-founder of LUBIS EDA. “Formal verification has the rigor to meet that challenge — but scaling it requires more than tools or individual expertise. FormalOS gives teams a systematic path from verification intent to confident sign-off.”
FormalOS is deployed within customers’ verification environments as part of LUBIS formal verification engagements and is currently being implemented across the company’s active projects. LUBIS engineers work alongside customer teams to apply the platform, methodology and automation to each project, combining FormalOS infrastructure with expert guidance throughout the verification flow.
Within today’s deployment model, FormalOS does not include, host or call any AI technology by default. It provides an interface through which customers can connect an AI model or LLM of their choice, along with AI skills that encode elements of LUBIS methodology for use when a model is connected. Customers decide whether to enable AI, which model to use, and how it operates within their verification environment.
Visit the FormalOS product page to learn more or request a demo.
LUBIS at Verification & Semiconductor Futures
LUBIS will introduce FormalOS to the chip design community at the Verification & Semiconductor Futures Conference in Austin on Oct. 6 and San Jose on Oct. 8, exhibiting at both events.
On the technical program, Dr. Tobias Ludwig will present “From Craft to System: A Platform Approach to Structured and Automated Formal Verification” at 11 a.m. local time at both events. The presentation explores the distinction between the expert judgment that only formal verification specialists can provide and the orchestration overhead around that work. Ludwig also examines how AI and automation can safely take on that overhead, freeing engineers to focus on the work that requires human discernment.
About the LUBIS Proven Process
The LUBIS Proven Process is a five-stage formal verification methodology designed to bring greater consistency, structure and predictability to complex verification programs.
The methodology is published and available as a free LUBIS Proven Process guide for chip design and verification teams.
About LUBIS EDA GmbH
LUBIS EDA empowers chip design teams to achieve high-confidence RTL sign-off with a systematic, scalable approach to formal verification. Through expert services and proven methodology, LUBIS helps engineering teams reduce tapeout risk, increase schedule predictability and scale the power of formal beyond individual experts.
The LUBIS Proven Process distills years of formal verification expertise into a mature, published methodology designed to bring greater consistency and structure to complex verification programs. Across more than 325 SoC, ASIC and IP sign-off projects, LUBIS has uncovered more than 900 critical design bugs that simulation missed.
LUBIS is headquartered in Kaiserslautern, Germany, with customers around the globe. Learn more at https://lubis-eda.com.
Photos accompanying this announcement are available at:
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Media Contact McKenzie Ross | LUBIS EDA | mckenzie.ross@lubis-eda.com
